Debbabi, Mourad (Autor)
Hassaïne, Fawzi (Autor)
Jarraya, Yosr (Autor)
Soeanu, Andrei (Autor)
Alawneh, Luay (Autor)
Verification and Validation in Systems Engineering
Assessing UML/SysML Design Models
Beschreibung
Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle.
Produktdetails
| ISBN/GTIN | 978-3-642-15228-3 |
|---|---|
| Seitenzahl | 248 S. |
| Kopierschutz | mit Wasserzeichen |
| Dateigröße | 8856 Kbytes |